An efficient multiplierless FIR filter chip with variable-length taps

The paper proposes a novel VLSI architecture for a multiplierless FIR filter chip providing variable length taps. To change the number of taps, we propose two special features called a data reuse structure and a recurrent coefficient scheme. These features consist of several MUXs and registers and reduce the number of gates over 20% compared with existing chips using an address generation unit and a module unit. Since multipliers occupy a large VLSI area, a multiplierless filter chip meeting real time requirement can save a large area. We propose a modified bit serial multiplication algorithm to compute two partial products in parallel, and thus, the proposed filter is twice as fast and has smaller hardware than previous multiplierless filters. We developed Verilog HDL models and performed logic synthesis using the CADENCE^TM CAD tool with the Hyundai^TM 0.8 μm SOG (sea-of-gate) cell library. The chip has only 9507 gates, was fabricated, and is running at 77 MHz