Title :
An Efficient Scan Chain Partitioning Scheme with Reduction of Test Data under Routing Constraint
Author :
Seok, Geewhun ; Lee, Il-Soo ; Ambler, Tony ; Womack, B.F.
Author_Institution :
Dept. of Electr. & Comput. Eng., Austin Univ., TX
Abstract :
A proposed scan chain partitioning scheme considers reduction of test set and test time, and the optimal routing inside each partitioned scan chain. First, two compatible scan cells are searched in input test set. One group of compatible scan cells is included in one partitioned scan chain, while the other group is in the other scan chain. In finding these compatible scan cells, the group-based approach is employed since it provides more optimal routing solution among the compatible scan cells in each of these two scan chains. After these two scan chains are filled with compatible scan cells, they are able to share one of two compatible columns in input test set only during the shift-in process. Therefore, one of two compatible columns can be omitted from input test set and the scan operation. Results with ISCAS´89 benchmark circuits show that proposed method could reduce test data volume by 25-33% compared with a normal multiple scan design
Keywords :
boundary scan testing; data reduction; logic partitioning; logic testing; network routing; compatible scan cells; group-based approach; optimal routing solution; routing constraint; scan chain partitioning scheme; shift-in process; Benchmark testing; Circuit faults; Circuit testing; Costs; Data engineering; Encoding; Integrated circuit testing; Pins; Routing; Test equipment;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2006. DFT '06. 21st IEEE International Symposium on
Conference_Location :
Arlington, VA
Print_ISBN :
0-7695-2706-X
DOI :
10.1109/DFT.2006.14