Quantifying the impact of current-sensing on interconnect delay trends

This work tries to compare the performance of traditionally used repeaters with a recently proposed differential current-sensing signaling technique for present and future technologies. Several technology scaling models have been proposed for device and interconnect scaling. For this study, the Berkeley predictive technology model, the semiconductor industry association model and the Sylvester-Keutzer model are used. Percentage of chip reached in a clock cycle is used as a metric. This allows a better understanding of the impact of these circuit techniques on architecture and floorplanning issues. Results show that differential current-sensing signaling is significantly faster than repeaters for most of the scaling theories and hence allows for a larger coverage of chip in a clock cycle. If clock rates are scaled more aggressively (as they have been in the past), the gains for current-sensing can be even more significant. Any new circuit style presents design challenges and potential power and area tradeoffs. Despite these challenges, and as a motivation to overcome them, this paper shows a methodology and preliminary results that indicate opportunities for novel interconnect circuits.