DocumentCode :
2906644
Title :
A zero-overhead dynamic optically reconfigurable gate array
Author :
Watanabe, Minoru ; Kobayashi, Fuminori
Author_Institution :
Dept. of Syst. Innovation & Informatics, Kyushu Inst. of Technol., Fukuoka, Japan
fYear :
2005
fDate :
11-14 Dec. 2005
Firstpage :
297
Lastpage :
298
Abstract :
This paper presents a zero-overhead dynamic optically reconfigurable gate array (DORGA) that uses the load capacitance of gates to construct a gate array to maintain its state during optical reconfiguration, and uses junction capacitance of photodiodes as configuration memory. It improves a reconfiguration overhead problem of the previously proposed DORGA. The reconfiguration procedure is executable without the overhead of optical reconfiguration by reducing the dispersion delay between optical reconfiguration circuits. This paper presents the design of 1,632 gate count zero-overhead DORGAs reduced the dispersion delay using a standard 0.35 μm three-metal CMOS process technology.
Keywords :
CMOS logic circuits; logic design; photodiodes; programmable logic arrays; reconfigurable architectures; CMOS process; configuration memory; dispersion delay; gate load capacitance; optical reconfiguration circuits; photodiode junction capacitance; zero overhead dynamic optically reconfigurable gate array; CMOS process; CMOS technology; Capacitance; Circuits; Delay effects; Optical arrays; Optical design; Optical devices; Photodiodes; Pulse measurements;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field-Programmable Technology, 2005. Proceedings. 2005 IEEE International Conference on
Print_ISBN :
0-7803-9407-0
Type :
conf
DOI :
10.1109/FPT.2005.1568569
Filename :
1568569
Link To Document :
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