A 500 kS/s 8-bit charge recycle based 2-bit per step SAR-ADC

Author

Shrivastava, Prasun ; Bhat, K.G. ; Laxminidhi, T. ; Bhat, M.S.

Author_Institution

Dept. of Electron. & Commun., Nat. Inst. Of Technol. Karnataka, Surathkal, India

fYear

2012

fDate

Nov. 30 2012-Dec. 1 2012

Firstpage

462

Lastpage

466

Abstract

This paper presents a low power 3.3 V, 500 kS/s 8bit successive approximation register ADC in 0.18μm technology. The DAC architecture employs charge recycling to produce 2-bits in one cycle i.e, it takes N/2 clock cycles to generate N-bits. The DAC architecture uses four rail to rail unity gain buffers and seven unit size capacitors in which one is half of the unit size to design ADC. Three comparators have been used to decide the 2-bits in each cycle. The simulated SNDR, at the input frequency of 56.64 kHz, is 48.14 dB and at 232.42 kHz is 47.03 dB. The simulated maximum INL as well as DNL is 0.5 LSB. The design consumes a low power of 1.8mW from the power supply of 3.3 V.

Keywords

buffer circuits; capacitors; digital-analogue conversion; DAC architecture; SAR-ADC; charge recycling; frequency 232.42 kHz; frequency 56.64 kHz; low power successive approximation register ADC; power 1.8 mW; rail to rail unity gain buffers; size 0.18 mum; unit size capacitors; voltage 3.3 V; word length 8 bit; Capacitors; Clocks; Computer architecture; Latches; Recycling; Switches; Transistors; 2-bit per step; Charge Recycling; Latch based comparator; Low power; SAR ADC; Unity Gain Buffer;

fLanguage

English

Publisher

ieee

Conference_Titel

Emerging Applications of Information Technology (EAIT), 2012 Third International Conference on

Conference_Location

Kolkata

Print_ISBN

978-1-4673-1828-0

Type

conf

DOI

10.1109/EAIT.2012.6408018

Filename

6408018