Design of low power fault tolerant reversible multiplexer using QCA

Reversible logic has emerged as a promising computing paradigm having its applications in low power CMOS design, quantum computing and nanotechnology in recent years. In this paper a fault tolerant reversible multiplexer (MUX) has been proposed using a parity preserving Fredkin gate for the first time. Proposed 2:1 MUX has been designed using only one Fredkin gate which has produced two garbage outputs. The proposed parity preserving reversible multiplexer circuit is more efficient in power dissipation and fault tolerance. It should be a promising step towards the low power, nano-scale circuit design for the future generation quantum computer.