DocumentCode :
2906852
Title :
A state-serial Viterbi decoder architecture for digital radio on FPGA
Author :
Petrov, Mihail ; Glesner, Manfred
Author_Institution :
Inst. of Microelectron. Syst., Darmstadt Univ. of Technol.
fYear :
2005
fDate :
11-14 Dec. 2005
Firstpage :
323
Lastpage :
324
Abstract :
This paper proposes an area-efficient Viterbi decoder architecture for digital radio receivers, which exploits the new features offered by modern FPGA. Implementation results show that our architecture meets the throughput requirements for the DAB and DRM standards, while consuming extremely few hardware resources
Keywords :
Viterbi decoding; digital radio; field programmable gate arrays; logic design; radio receivers; standards; DAB standards; DRM standards; digital radio receivers; field programmable gate arrays; state-serial Viterbi decoder architecture; Computer architecture; Convolutional codes; Counting circuits; Decoding; Digital communication; Field programmable gate arrays; Hardware; Read-write memory; Shift registers; Viterbi algorithm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field-Programmable Technology, 2005. Proceedings. 2005 IEEE International Conference on
Conference_Location :
Singapore
Print_ISBN :
0-7803-9407-0
Type :
conf
DOI :
10.1109/FPT.2005.1568582
Filename :
1568582
Link To Document :
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