Implementation of Gabor-type filters on field programmable gate arrays

Although biological visual systems have been widely studied at the physiological, psychophysical and functional levels, our understanding of its signal processing mechanisms is still very rudimentary. One of the obstacles in this process is the difficulty of dealing with the vast amounts of processing necessary to test real-time temporal models of the visual system. In this paper, we first present a high performance FPGA-based cellular neural network which implements a Gabor-type filter. This is a building block element which we intend to use with different parameters to model cells in V1. The application of the Gabor-type filter in a neuromorphic system consisting of an analog VLSI retina chip interfaced to our Gabor chip is also presented. The retina chip serves as an imager and transmits its output to the FPGA via an address event representation (AER) transceiver (Boahen, 2000). Using AER, multiple chips can be interconnected in a modular network to form large networks of Gabor chips. By combining both analog VLSI chips and digital chips (e.g. DSP chips, microprocessors, and FPGA chips), we hope to make real-time implementations of early vision models and visualize their temporal behaviour, while achieving a level of performance, integration, power consumption, area and flexibility not possible using any technology in isolation