Title :
A 2.24GHz Wide Range Low Jitter DLL-Based Frequency Multiplier using PMOS Active Load for Communication Applications
Author :
Lin, Chih-Hsing ; Chiu, Ching-Te
Author_Institution :
Dept. of Commun. Eng., National Tsing Hua Univ., Hsin-Chu
Abstract :
In this paper, a wide-range DLL-based frequency multiplier with PMOS active load for communication applications is proposed. Adding the PMOS active load in the delay cells has the inductive-peaking effect to increase the operation frequency range. The DLL-based frequency multiplier uses simple exclusive-or (XOR) gates and phase blending technique for the frequency multiplications. The frequency multiplier can generate N times of frequency of the input clock when the number of delay cells (N) in the VCDL is even. The output frequency of the proposed frequency multiplier ranges from 80MHz to 2.24GHz using TSMC 0.18mum CMOS process. The locked time is 0.96ns locked time at 400MHz. The peak-to-peak jitter is 46ps at 80MHz and 95.3ps at 2.24GHz. The power consumption of proposed frequency multiplier is 25.79mW at 400MHz.
Keywords :
CMOS integrated circuits; delay lock loops; frequency multipliers; jitter; logic gates; 0.08 to 2.24 GHz; 0.18 micron; 0.96 ns; 25.79 mW; 46 ps; 95.3 ps; PMOS active load; communication applications; delay cells; delay lock loop; exclusive-or gates; frequency multiplications; inductive-peaking effect; phase blending technique; wide range low jitter DLL-based frequency multiplier; Application specific integrated circuits; CMOS technology; Clocks; Delay effects; Delay lines; Energy consumption; Frequency conversion; Frequency synchronization; High speed integrated circuits; Jitter;
Conference_Titel :
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location :
New Orleans, LA
Print_ISBN :
1-4244-0920-9
Electronic_ISBN :
1-4244-0921-7
DOI :
10.1109/ISCAS.2007.377888
