Net power directed clustering algorithm for low net-power implementation of FPGAs

The goal of our technique is to reduce the capacitance on high power consuming nets by including as many of these nets as possible inside CLB (configurable logic block) clusters wherein they can be routed on low capacitance lines. The work presented here is an extension of previous work whereby we incorporate net power estimations into the metrics for identifying the power critical nets in the circuit. The results of our technique show an average reduction of 37% in the net power over that achieved by Xilinx´s ISE 5.3i tools using default settings