DocumentCode :
2906961
Title :
A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates
Author :
Dechu, Sandeep ; Goparaju, Manoj Kumar ; Tragoudas, Spyros
Author_Institution :
Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL
fYear :
2006
fDate :
4-6 Oct. 2006
Firstpage :
318
Lastpage :
326
Abstract :
Compared to CMOS logic gates, threshold logic gates are more susceptible to manufacturing inaccuracies. These inaccuracies may inadvertently affect the functionality of the gate. Hence it is very much important to consider the manufacturing defects during the design of gates using threshold logic principle. This paper defines a metric which indicates the degree of tolerance of a designed gate to the manufacturing inaccuracies. Experimental results have been presented for several gates
Keywords :
CMOS logic circuits; logic design; logic gates; threshold logic; CMOS logic gates; manufacturing defects; manufacturing inaccuracies; threshold logic gates; CMOS logic circuits; Computer aided manufacturing; FinFETs; Lithography; Logic circuits; Logic design; Logic devices; Logic gates; Optical bistability; Semiconductor process modeling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2006. DFT '06. 21st IEEE International Symposium on
Conference_Location :
Arlington, VA
ISSN :
1550-5774
Print_ISBN :
0-7695-2706-X
Type :
conf
DOI :
10.1109/DFT.2006.7
Filename :
4030943
Link To Document :
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