DocumentCode
2907110
Title
An integrated timing and dynamic supply noise verification for nano-meter CMOS SoC designs
Author
Shimazaki, Kenji ; Fukazawa, Mitsuya ; Nagata, Makoto ; Miyahara, Shingo ; Hirata, Masaaki ; Sato, Kazuhiro ; Tsujikawa, Hiroyuki
Author_Institution
Matsushita Electr. Ind. Co. Ltd., Nagaokakyo, Japan
fYear
2005
fDate
18-21 Sept. 2005
Firstpage
31
Lastpage
34
Abstract
A semidynamic timing analysis flow of dynamic drop consideration applicable to a large-scale circuit is proposed. This technique is compared not only with SPICE simulation but with measurements using built-in noise probing and on-chip delay monitoring techniques, which validates the proposed flow.
Keywords
CMOS integrated circuits; SPICE; integrated circuit noise; nanoelectronics; system-on-chip; SPICE simulation; built-in noise probing; dynamic supply noise verification; large-scale circuit; nanometer CMOS SoC designs; on-chip delay monitoring techniques; semidynamic timing analysis flow; Circuit noise; Delay estimation; Integrated circuit noise; Large-scale systems; Logic; Noise measurement; Power supplies; Semiconductor device measurement; Timing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
Print_ISBN
0-7803-9023-7
Type
conf
DOI
10.1109/CICC.2005.1568600
Filename
1568600
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