Title :
A VLSI Architecture for a Fast Computation of the 2-D Discrete Wavelet Transform
Author :
Yu Hu ; Qing Li ; Siwei Ma ; Kuo, C.-C Jay
Author_Institution :
Dept. of Electr. Eng., Southern California Univ., Los Angeles, CA
Abstract :
Video encoding to yield a decoder-friendly H.264 bit stream that consumes less decoding power yet with little coding efficiency degradation is investigated in this work. The in pipeline mode enhances the computing time by deblocking filters (ADF). We first propose a power among the three stages and by incorporating parallelism at encoder performs the rate-distortion-decoder complexity optimization (RDC) to save the decoder power needed for deblocking filter operations, which is called the decoder-friendly adaptive deblocking filter (DF-ADF) mode decision. The RDC optimization framework presents a way to balance coding efficiency and the ADF decoding cost in the mode decision process. The effectiveness of the proposed DF-ADF algorithm is demonstrated by experiments with diverse video contents and bit rates.
Keywords :
VLSI; discrete wavelet transforms; optimisation; video coding; 2D discrete wavelet H.264/AVC; VLSI architecture; fast computation; rate-distortion-decoder complexity optimization; video encoding; Adaptive filters; Computer architecture; Decoding; Degradation; Discrete wavelet transforms; Encoding; Parallel processing; Pipelines; Streaming media; Very large scale integration; 2-D discrete wavelet transform; VLSI architecture for fast computation; parallel processing; pipeline; real-time architecture;
Conference_Titel :
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location :
New Orleans, LA
Print_ISBN :
1-4244-0920-9
Electronic_ISBN :
1-4244-0921-7
DOI :
10.1109/ISCAS.2007.378672
