• DocumentCode
    2907366
  • Title

    Parity-Based Fault Detection Architecture of S-box for Advanced Encryption Standard

  • Author

    Kermani, Mehran Mozaffari ; Reyhani-Masoleh, Arash

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Western Ontario Univ., London, Ont.
  • fYear
    2006
  • fDate
    4-6 Oct. 2006
  • Firstpage
    572
  • Lastpage
    580
  • Abstract
    In this paper, the authors present parity-based fault detection architecture of the S-box for designing high performance fault detection structures of the advanced encryption standard. Instead of using look-up tables for the S-box and its parity prediction, logical gate implementations based on the composite field are utilized. After analyzing the error propagation for injected single faults, the authors modify the original S-box and suggest fault detection architecture for the S-box. Using the closed formulations for the predicted parity bits, the authors propose a parity-based fault detection scheme for reaching the maximum fault coverage. Moreover, the overhead costs, including space complexity and time delay of our modified S-box and the parity predictions are also compared to those of the previously reported ones
  • Keywords
    cryptography; error analysis; error detection; logic gates; parity check codes; S-box; advanced encryption standard; error propagation analysis; logical gate implementations; maximum fault coverage; parity bits; parity fault detection architecture; space complexity; time delay; Computer architecture; Costs; Cryptography; Delay effects; Electrical fault detection; Error analysis; Fault detection; Hardware; Polynomials; Table lookup;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance in VLSI Systems, 2006. DFT '06. 21st IEEE International Symposium on
  • Conference_Location
    Arlington, VA
  • ISSN
    1550-5774
  • Print_ISBN
    0-7695-2706-X
  • Type

    conf

  • DOI
    10.1109/DFT.2006.50
  • Filename
    4030970