DocumentCode :
2907376
Title :
Global Built-In Self-Repair for 3D memories with redundancy sharing and parallel testing
Author :
Wang, Xiaodong ; Vasudevan, Dilip ; Lee, Hsien-Hsin S.
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
fYear :
2012
fDate :
Jan. 31 2012-Feb. 2 2012
Firstpage :
1
Lastpage :
8
Abstract :
3D integration is a promising technology that provides high memory bandwidth, reduced power, shortened latency, and smaller form factor. Among many issues in 3D IC design and production, testing remains one of the major challenges. This paper introduces a new design-for-test technique called 3D-GESP, an efficient Built-In-Self-Repair (BISR) algorithm to fulfill the test and reliability needs for 3D-stacked memories. Instead of the local testing and redundancy allocation method as most current BISR techniques employed, we introduce a global 3D BISR scheme, which not only enables redundancy sharing, but also parallelizes the BISR procedure among all the stacked layers of a 3D memory. Our simulation results show that our proposed technique will significantly increase the memory repair rate and reduce the test time.
Keywords :
built-in self test; design for testability; integrated circuit design; integrated circuit testing; random-access storage; three-dimensional integrated circuits; 3D IC design; 3D IC production; 3D IC testing; 3D integration; 3D-GESP; 3D-stacked memories; design-for-test technique; global 3D BISR scheme; global built-in self-repair algorithm; local testing; memory repair; parallel testing; redundancy allocation method; redundancy sharing; test time reduction; Built-in self-test; Circuit faults; Computer architecture; Decoding; Maintenance engineering; Redundancy;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
3D Systems Integration Conference (3DIC), 2011 IEEE International
Conference_Location :
Osaka
Print_ISBN :
978-1-4673-2189-1
Type :
conf
DOI :
10.1109/3DIC.2012.6262967
Filename :
6262967
Link To Document :
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