• DocumentCode
    2907384
  • Title

    A 0.14mW/Gbps high-density capacitive interface for 3D system integration

  • Author

    Fazzi, Alberto ; Magagni, Luca ; Mirandola, Mauro ; Canegallo, Roberto ; Schmitz, Stefan ; Guerrieri, Roberto

  • Author_Institution
    Adv. Res. Center on Electron. Syst., Bologna Univ., Italy
  • fYear
    2005
  • fDate
    18-21 Sept. 2005
  • Firstpage
    101
  • Lastpage
    104
  • Abstract
    This paper presents a synchronous 3D interconnection based on capacitive coupling. The designed link presents a power consumption of 0.128mW/pin@975Mbps/pin, overcoming standard I/O pads performance of two orders of magnitude. High bit-rate, reduced power consumption and electrode area down to 8×8μm2 enable the implementation of highly parallel pipelined interfaces for inter-chip communication, with an aggregate consumption of about 0.14mW/Gbps.
  • Keywords
    integrated circuit interconnections; 3D interconnection; 3D system integration; capacitive coupling; capacitive interface; electrode area; inter-chip communication; power consumption; Assembly; Clocks; Couplings; Electrodes; Energy consumption; Integrated circuit interconnections; Multiplexing; Power system interconnection; Synchronization; Transmitters;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
  • Print_ISBN
    0-7803-9023-7
  • Type

    conf

  • DOI
    10.1109/CICC.2005.1568618
  • Filename
    1568618
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2907384