A novel error correction technique for adjacent errors

Memories are one of the most widely used elements in electronic systems, and their reliability when exposed to Single Events Upsets (SEUs) has been studied extensively. As transistor sizes shrink, Multiple Bits Upsets (MBUs) are becoming an increasingly important factor in the reliability of memories exposed to radiation effects. To address this issue, Built-in Current Sensors (BICS) or Parity codes have recently been applied in conjunction with Single Error Correction/Double Error Detection (SEC-DED) codes to protect memories from MBUs. In this paper, this approach is taken one step further, proposing specific codes optimized to provide protection against errors in adjacent bits in memories. By exploiting the locality of errors within an MBU and the error detection and location capabilities of parity codes, the proposed codes result in both a better protection level and a reduced cost. This techniques improves memory´s reliability by 40X compared to Hamming Codes (HC) and 2X the MTTF compared to Reed Muller Codes (RMC) for clustered MBUs.