Transistor sizing and folding techniques for radiation hardening

Author

Kastensmidt, F. Lima ; Assis, T. ; Ribeiro, I. ; Wirth, G. ; Brusamarello, L. ; Reis, R.

Author_Institution

Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil

fYear

2009

fDate

14-18 Sept. 2009

Firstpage

512

Lastpage

519

Abstract

The efficiency of transistor sizing and folding techniques to mitigate SET in CMOS circuits is evaluated using circuit and device simulations. According to the LET of the ionizing particle, the SET can be more or less filtered by these methods. Based on the results of the circuit and device simulations, a novel technique able to reduce the SET effect is proposed. The method combines transistor sizing, folding and resistors. The technique was applied in a chain of inverters and SRAM cell.

Keywords

CMOS integrated circuits; MOSFET; SRAM chips; circuit simulation; invertors; radiation hardening (electronics); CMOS circuits; SET effect; SRAM cell; circuit simulations; folding techniques; inverters; ionizing particle; radiation hardening; resistors; transistor sizing techniques; Integrated circuit modeling; Inverters; Ions; Logic gates; Random access memory; Semiconductor process modeling; Transistors; SET; fault tolerance; microelectronics; radiation effects; radiation hardening; transistor folding;

fLanguage

English

Publisher

ieee

Conference_Titel

Radiation and Its Effects on Components and Systems (RADECS), 2009 European Conference on

Conference_Location

Bruges

ISSN

0379-6566

Print_ISBN

978-1-4577-0492-5

Electronic_ISBN

0379-6566

Type

conf

DOI

10.1109/RADECS.2009.5994705

Filename

5994705