Title :
Electrical, thermal and mechanical impact of 3D TSV and 3D stacking technology on advanced CMOS devices — Technology directions
Author_Institution :
IMEC, Leuven, Belgium
fDate :
Jan. 31 2012-Feb. 2 2012
Abstract :
3D integration technology using thin die and Through-Silicon-Via, TSV, connections affect transistor and circuit behavior through electrical, mechanical and thermal interactions. The roadmap for further 3D technology development should focus on minimizing these effects.
Keywords :
CMOS integrated circuits; integrated circuit interconnections; three-dimensional integrated circuits; 3D TSV; 3D stacking technology; 3D technology development; CMOS devices; circuit behavior; electrical interaction; mechanical interaction; thermal interaction; through silicon vias; Silicon; Stacking; Stress; Temperature measurement; Thermal resistance; Through-silicon vias;
Conference_Titel :
3D Systems Integration Conference (3DIC), 2011 IEEE International
Conference_Location :
Osaka
Print_ISBN :
978-1-4673-2189-1
DOI :
10.1109/3DIC.2012.6262977
