Title :
An improved "soft" eFPGA design and implementation strategy
Author :
Aken´Ova, Victor ; Lemieux, Guy ; Saleh, Resve
Author_Institution :
Dept. of Electr. & Comput. Eng., British Columbia Univ., Vancouver, BC, Canada
Abstract :
A recently proposed "soft" eFPGA methodology was used to create small amounts of programmable logic using the ASIC flow, but it incurs significant overhead. In this paper, it is shown that architecture-specific tactical standard cells can reduce the area and delay overhead of the previous approach by 58% and 40% respectively. It is also shown that by imposing a structured design and layout approach, the logic capacity and quality of standard-cell-based eFPGAs can be significantly improved. Finally, it is shown that our improved ASIC flow approach can create layouts that are competitive with another approach called GILES that uses custom FPGA CAD tools and nonstandard cells for tile layout purposes.
Keywords :
application specific integrated circuits; field programmable gate arrays; integrated circuit design; logic design; programmable logic devices; ASIC flow; FPGA CAD tools; GILES that; architecture-specific tactical standard cells; delay overhead; eFPGA design; logic capacity; logic quality; programmable logic; Application specific integrated circuits; Costs; Delay; Fabrics; Field programmable gate arrays; Libraries; Logic design; Programmable logic arrays; Programmable logic devices; Tiles;
Conference_Titel :
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
Print_ISBN :
0-7803-9023-7
DOI :
10.1109/CICC.2005.1568636
