Look-up table leakage reduction for FPGAs

We propose new programmable FPGA look-up tables (LUTs) that can operate in two different modes: high-performance or low-power. Selection between the two modes is realized by an extra SRAM cell that can be shared by a number of LUTs. In high-performance mode, the LUTs provide similar power and performance to a conventional LUT. In low-power mode, one LUT reduces leakage by 53%, while another reduces leakage by 53% and 80% when outputting a logic-0 and logic-1 respectively, which can lead to an average leakage reduction of up to 76%. In low-power mode, delay is increased by 5% to 20% compared to a conventional LUT. The technique scales well and reduces further leakage for new FPGA architectures that use larger size LUTs.