Title :
A high performance, high voltage output buffer in a low voltage CMOS process
Author :
Chauhan, Rajat ; Rajagopal, Karthik ; Menezes, Vinod ; Roopashree, H.M. ; Jacob, Sanish Koshy
Author_Institution :
Texas Instruments India Pvt. Ltd., Karnataka, India
Abstract :
The proposed output buffer circuit uses 1.8V transistors in 90nm CMOS process to develop I/Os for 2.5V and 3.3V interfaces. A voltage clamp circuit, bias generators, and a feedback circuit are used to ensure reliability and noise decoupling. Use of these circuits enables achieving low power (130μA) and high performance (up to 275MHz) in a comparative area of an equivalent I/O in 90nm 3.3V process.
Keywords :
CMOS analogue integrated circuits; buffer circuits; circuit feedback; integrated circuit design; low-power electronics; 1.8 V; 130 muA; 2.5 V; 3.3 V; 90 nm; CMOS process; I/O buffer; bias generators; feedback circuit; high speed interfaces; high voltage design; noise decoupling; output buffer circuit; voltage clamp circuit; CMOS process; Capacitors; Coupling circuits; Driver circuits; Feedback circuits; Impedance; Instruments; Jacobian matrices; Low voltage; Threshold voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
Print_ISBN :
0-7803-9023-7
DOI :
10.1109/CICC.2005.1568648
