Title :
A 333MHz random cycle DRAM using the floating body cell
Author :
Hatsuda, Kosuke ; Fujita, Katsuyuki ; Ohsawa, Takashi
Author_Institution :
SoC R&D Center, Toshiba Corp. Semicond. Co., Yokohama
Abstract :
A Monte Carlo simulation shows that a DRAM using the floating body cell (FEC) realizes a 333MHz high-speed random cycle with an introduction of a symmetrical sense amplifier circuit and optimization of its current mirror ratio. Since the FEC DRAM having a superior affinity with logic LSI process is also shown to have its macro size smaller than the conventional 1T-1C DRAM, the FEC is a promising candidate for next generation embedded DRAM cells
Keywords :
DRAM chips; Monte Carlo methods; amplifiers; circuit optimisation; high-speed integrated circuits; large scale integration; 333 MHz; FEC DRAM circuits; Monte Carlo simulation; current mirror ratio optimization; embedded DRAM cells; floating body cell; high-speed random cycle; logic LSI process; random cycle DRAM; symmetrical sense amplifier circuit; Capacitors; Circuits; Contact resistance; Immune system; Parasitic capacitance; Random access memory; Research and development; Semiconductor optical amplifiers; Signal restoration; Tin;
Conference_Titel :
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
Conference_Location :
San Jose, CA
Print_ISBN :
0-7803-9023-7
DOI :
10.1109/CICC.2005.1568656
