Reconfigurable Software Defined Payload architecture that reduces cost and risk for various missions

Harris has been delivering multi-processor based Software Defined Payloads (SDP) since 1998 resulting in a development path from RISC processor-based architectures to FPGA-based architectures. This paper presents implementations of Software Defined Radios (SDR) and payloads using this architecture. The modularity of this approach where size, weight, and power can be traded for increased performance is leading the way in responsive and flexible space payloads. The Harris SDP platform, powered by four Xilinx Virtex 4 Field Programmable Gate Arrays (FPGAs), includes a Single Event Effect (SEE) mitigation scheme to provide the radiation hardened horsepower to support the baseline mission. For the NASA CoNNeCT program, Harris extended this platform into a high data rate 100 Mbps software defined radio. This FPGA-based architecture will be described which provides a flexible, scalable core to support a multitude of payload missions in addition to Space Telecommunications Radio System (STRS) compliant communications missions. The power and flexibility of this architecture was demonstrated with a software defined radar payload. STRS as well as standard interfaces enable third party software, firmware, and hardware compatibility. The processing performance and bandwidth available in the Harris architecture enables software defined mission payloads to be quickly developed for remote sensing, surveillance, tracking, and beyond.