Design of an Extended Floating-Point Multiply-Add-Fused Unit for Exploiting Instruction-Level Parallelism

This paper presents an extended single-precision floating-point multiply-add-fused unit, called EMAF unit, which is designed for exploiting instruction-level parallelism. Concurrent addition and multiplication instructions can be executed in parallel besides traditional multiply-add-fused instructions. Moreover, some other kinds of two consecutive but dependent instructions can also be accelerated without stalling anyone. At the same time the accuracy is also increased over the traditional multiply-add-fused units. The EMAF unit is implemented with three pipeline stages. Experiment results show that compared with the traditional multiply-add-fused unit up to 26% cycle reduction is gained at the cost of 0.1 ns time penalty.