Title :
Design considerations for 2nd-order and 3rd-order bang-bang CDR loops
Author :
Wang, Shoujun ; Mei, Haitao ; Baig, Mashkoor ; Bereza, William ; Kwasniewski, Tad ; Patel, Rakesh
Author_Institution :
Altera Corp., Kanata, Ont.
Abstract :
This paper examines two popular bang-bang CDR architectures: one is with a conventional RC loop filter which often involves a 3rd order loop design and the other is with a separate proportional path which involves a straightforward 2nd order loop design. Design considerations for the two architectures are compared as a function of various design parameters that impact jitter tolerance. Theoretical findings are confirmed by experimental results of a wide-range bang-bang CDR fabricated in 90nm CMOS
Keywords :
CMOS digital integrated circuits; RC circuits; active filters; clocks; integrated circuit design; 2nd order loop design; 2nd-order bang-bang CDR loop; 3rd order loop design; 3rd-order bang-bang CDR loops; 90 nm; CMOS technology; RC loop filter; bang-bang CDR architecture; clock and data recovery circuits; jitter tolerance; wide-range bang-bang CDR; Capacitors; Circuits; Clocks; Filters; Frequency; Jitter; Phase detection; Resistors; Stability; Voltage-controlled oscillators;
Conference_Titel :
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
Conference_Location :
San Jose, CA
Print_ISBN :
0-7803-9023-7
DOI :
10.1109/CICC.2005.1568669
