Title :
Fabrication and bonding process of fine pitch Cu pillar bump on thin Si chip for 3D stacking IC
Author :
Ki, Won-Myoung ; Kang, Myong-Suk ; Yoo, Sehoon ; Lee, Chang-Woo
Author_Institution :
Electron. Packaging Eng., Univ. of Sci. & Technol., Daejeon, South Korea
fDate :
Jan. 31 2012-Feb. 2 2012
Abstract :
3D packaging technology has been studied actively due to requirement of high performance, high density, and multifunction on electronic devices. This study investigated formation and bonding process of ultra-fine Cu pillar bump on both sides of Si thin wafer for 3D IC. Thickness of the thin wafer was 100μm. The bumps for the interconnection were formed as Sn-3.5Ag cap bump on Cu pillar bump by electroplating method. The diameter and height of the bump were 20μm, respectively. Thin Si chip was joined at bonding load 1.5N and bonding temperature 260°C by flip-chip bonder and then reflow process was added for 15~20 seconds at 260°C. After reflow process, thickness of IMCs in the Sn/Cu pillar interface was nearly the same compared with only flip-chip bonding method. And the effect of self-alignment was found.
Keywords :
copper; electroplating; elemental semiconductors; flip-chip devices; integrated circuit interconnections; silicon; three-dimensional integrated circuits; tin; wafer bonding; wafer level packaging; 3D packaging technology; 3D stacking IC; Si; Sn-Cu; bonding load; bonding process; bonding temperature; electronic devices; electroplating method; flip-chip bonding method; reflow process; silicon chip; silicon thin wafer; size 100 mum; size 20 mum; temperature 260 degC; time 15 s to 20 s; tin-copper pillar interface; ultrafine-pitch copper pillar bump; Bonding; Films; Flip chip; Glass; Joints; Silicon; Through-silicon vias;
Conference_Titel :
3D Systems Integration Conference (3DIC), 2011 IEEE International
Conference_Location :
Osaka
Print_ISBN :
978-1-4673-2189-1
DOI :
10.1109/3DIC.2012.6263016
