A performance optimized CMOS distributed LNA for UWB receivers

Author

Heydari, Payam ; Lin, Denis

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Irvine, CA, USA

fYear

2005

fDate

18-21 Sept. 2005

Firstpage

337

Lastpage

340

Abstract

This paper presents the design and implementation of a performance-optimized LNA circuit targeted for UWB receivers. The systematic design of a CMOS distributed LNA circuit comprising cascode cells is illustrated. Each cascode cell employs an inductor between the common-source and common-gate devices to enhance the bandwidth, while reducing the high-frequency input-referred noise. A three-stage performance optimized LNA has been fabricated in Jazz´s sbc18 0.18μm SiGe process, while using MOS transistors only. Measurements of the LNA circuit show a 2.9-dB noise figure and a forward gain of 8dB over the 7.5GHz UWB bandwidth. The circuit exhibits an IIP3 of -3.4dBm.

Keywords

CMOS analogue integrated circuits; Ge-Si alloys; circuit optimisation; distributed amplifiers; integrated circuit design; low noise amplifiers; radio receivers; ultra wideband communication; wideband amplifiers; 0.18 micron; 7.5 GHz; 8 dB; CMOS distributed LNA circuit; LNA circuit optimization; MOS transistors; SiGe; UWB receivers; cascode cells; low noise amplifiers; noise reduction; performance optimization; three stage LNA; Bandwidth; Circuit noise; Gain measurement; Germanium silicon alloys; Inductors; MOSFETs; Noise figure; Noise measurement; Noise reduction; Silicon germanium;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005

Print_ISBN

0-7803-9023-7

Type

conf

DOI

10.1109/CICC.2005.1568674

Filename

1568674