DocumentCode :
2908334
Title :
Robust multi-GHz (7.4GHz) on-chip image rejection in CMOS
Author :
Baki, Rola A. ; El-Gamal, Mourad N.
Author_Institution :
RFIC Lab., McGill Univ., Montreal, Que.
fYear :
2005
fDate :
21-21 Sept. 2005
Firstpage :
341
Lastpage :
344
Abstract :
The implementation of a robust, unconditionally stable, and high-Q image reject filter in standard CMOS is presented, enabling the realization of on-chip heterodyne receivers at 5 GHz and beyond. We propose the use of two cascaded notch filters, with slightly offsetted frequencies, resulting in a wide rejection bandwidth, thus eliminating the overhead of automatic tuning. A single-notch prototype achieves 62 dB of rejection at 7.4 GHz, and a double-notch design achieves 30 dB of rejection over 400 MHz
Keywords :
CMOS integrated circuits; cascade networks; circuit stability; circuit tuning; integrated circuit design; low noise amplifiers; notch filters; radio receivers; system-on-chip; 5 GHz; 7.4 GHz; CMOS process; automatic tuning; cascaded notch filters; double notch filter; high-Q image reject filter; on-chip heterodyne receiver; on-chip image rejection; single notch filter; wide rejection bandwidth; CMOS technology; Circuit optimization; Energy consumption; Equations; Filters; Image analysis; Radio frequency; Robustness; Transfer functions; Zinc;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
Conference_Location :
San Jose, CA
Print_ISBN :
0-7803-9023-7
Type :
conf
DOI :
10.1109/CICC.2005.1568675
Filename :
1568675
Link To Document :
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