A /spl Delta//spl Sigma/ DAC with reduced activity data weighted averaging and anti-jitter digital filter

Author

Bicakci, Ara ; Singh, Gurjinder

Author_Institution

LSI Logic Corp., Milpitas, CA

fYear

2005

fDate

21-21 Sept. 2005

Firstpage

383

Lastpage

386

Abstract

A CMOS DAC with a 4th order digital DeltaSigma modulator achieves more than 94dB SFDR and 84dB SNDR for a conversion bandwidth of 2.2MHz and an over-sampling ratio of eight. A post modulator digital FIR filter increases jitter immunity and a reduced activity data-weighted-averaging (RADWA) scheme improves SFDR without any noticeable degradation in the SNDR. The prototype chip that contains the RA-DWA circuitry, the core analog DAC, and the clock generation circuitry is built in 0.13 mum standard digital CMOS process. The analog and digital power consumptions are 70mW and 2mW respectively. The DAC area is 1times1.2 mm²

Keywords

CMOS integrated circuits; FIR filters; delta-sigma modulation; jitter; 0.13 micron; 2 mW; 2.2 MHz; 70 mW; DeltaSigma DAC; RA-DWA circuit; anti-jitter digital filter; clock generation circuit; clock generation circuitry; core analog DAC; digital CMOS process; jitter immunity; post modulator digital FIR filter; reduced activity data-weighted-averaging; Bandwidth; Circuits; Clocks; Degradation; Delta modulation; Digital filters; Digital modulation; Finite impulse response filter; Jitter; Prototypes;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005

Conference_Location

San Jose, CA

Print_ISBN

0-7803-9023-7

Type

conf

DOI

10.1109/CICC.2005.1568685

Filename

1568685