DocumentCode
2908542
Title
Design of 3D-IC for butterfly NOC based 64 PE-multicore: Analysis and design space exploration
Author
Hammami, O. ; M´zah, A. ; Hamwi, K.
Author_Institution
ENSTA ParisTech, Paris, France
fYear
2012
fDate
Jan. 31 2012-Feb. 2 2012
Firstpage
1
Lastpage
4
Abstract
3D Conception is an efficient solution to deal with the global wiring delay which is overcoming the gates delay in nanometres CMOS technology. We present in this paper, the implementation of a butterfly NOC based 64 PE multicore using 3D-IC Tezzaron technology. In order to design a 3D NOC, we present different partionning configurations. Thanks to the 3D implementation with 2 tiers, we reduced the area of the chip to the half and we reduced the long interconnect delay.
Keywords
CMOS integrated circuits; delays; integrated circuit design; integrated circuit interconnections; multiprocessing systems; network-on-chip; three-dimensional integrated circuits; 3D NoC design; 3D-IC Tezzaron technology; 3D-IC design; butterfly NoC based 64 PE-multicore; design space exploration; gates delay; global wiring delay; interconnect delay; nanometre CMOS technology; CMOS integrated circuits; Delay; Program processors; Routing; Solid modeling; Topology; 3D IC; 3D NoC; MPSoC; Tezzaron; butterfly;
fLanguage
English
Publisher
ieee
Conference_Titel
3D Systems Integration Conference (3DIC), 2011 IEEE International
Conference_Location
Osaka
Print_ISBN
978-1-4673-2189-1
Type
conf
DOI
10.1109/3DIC.2012.6263029
Filename
6263029
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