Title :
A 1.0 V 40mW 10b 100MS/s pipeline ADC in 90nm CMOS
Author :
Ishii, Hirotomo ; Tanabe, Ken ; Iida, Tetsuya
Author_Institution :
Semicond. Co., Toshiba Corp., Kawasaki
Abstract :
A 1.0V 10b 100MS/s pipeline ADC consuming 40mW fabricated in a 90nm CMOS process is described. Design consideration for the thermal noise of operational amplifiers effectively saves the power consumption of the ADC with conventional architecture at 1.0 V supply. Measured peak SNDR of the ADC is 56.5dB. It occupies 0.52 mm2 with on-chip decoupling capacitors and 0.31 mm2 without the capacitors, both of which includes the buffer for reference voltages
Keywords :
CMOS integrated circuits; analogue-digital conversion; buffer circuits; circuit noise; operational amplifiers; pipeline processing; thermal noise; 1.0 V; 40 mW; 90 nm; CMOS process; on-chip decoupling capacitors; operational amplifiers; pipeline ADC; power consumption; reference voltage; thermal noise; CMOS process; Capacitors; Circuits; Energy consumption; Error correction; Low voltage; Operational amplifiers; Pipelines; Sampling methods; Switches;
Conference_Titel :
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
Conference_Location :
San Jose, CA
Print_ISBN :
0-7803-9023-7
DOI :
10.1109/CICC.2005.1568688
