Title :
A Power-Scalable Switch-Based Multi-processor FFT
Author :
Mohd, B.J. ; Swartzlander, Earl E., Jr.
Author_Institution :
Qualcomm, Inc., San Diego, CA, USA
Abstract :
This paper examines the architecture, algorithm and implementation of a switch-based multi-processor realization of the fast Fourier transform (FFT). The architecture employs M processing elements (PEs), and provides a speedup of M compared with systems that use a single PE. An algorithm is provided to detect and resolve memory conflicts. A CMOS implementation of a four-PE processor is presented. The design is reconfigurable to compute various FFT sizes. The design power consumption is scalable based on the number of active PEs. The timing, area and power results are discussed.
Keywords :
CMOS integrated circuits; cache storage; digital arithmetic; fast Fourier transforms; hypercube networks; integrated circuit design; microprocessor chips; CMOS implementation; N-point radix-2 FFT algorithm; butterfly network; cache-FFT processor; fast Fourier transform; four-PE processor; memory conflict detection; memory conflict resolving; power consumption; power-scalable switch-based multiprocessor FFT algorithm; processing element; reconfigurable design; CMOS technology; Fast Fourier transforms; Frequency; Pipelines; Power dissipation; Process design; Random access memory; Read only memory; Switches; Timing; Conflict-free; DSP; FFT;
Conference_Titel :
Application-specific Systems, Architectures and Processors, 2009. ASAP 2009. 20th IEEE International Conference on
Conference_Location :
Boston, MA
Print_ISBN :
978-0-7695-3732-0
Electronic_ISBN :
2160-0511
DOI :
10.1109/ASAP.2009.18
