DocumentCode
2908601
Title
Dual scalable 500MS/s, 5b time-interleaved SAR ADCs for UWB applications
Author
Ginsburg, Brian P. ; Chandrakasan, Anantha P.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA
fYear
2005
fDate
21-21 Sept. 2005
Firstpage
403
Lastpage
406
Abstract
A dual 500MS/s, 5b ADC chip is implemented in a 0.18 mum CMOS process. The two ADCs have synchronized sampling for use in an I/Q UWB receiver. Each ADC has a 6-way time-interleaved successive approximation register topology and uses full custom logic, self-timed bit-cycling, and duty cycling of the comparator preamplifiers to enable 500MS/s operation with 7.8mW power consumption
Keywords
CMOS integrated circuits; analogue-digital conversion; integrated circuit design; radio receivers; ultra wideband communication; 0.18 micron; 5 bit; 7.8 mW; CMOS process; I-Q UWB receiver; comparator preamplifiers; dual scalable ADC chip; duty cycling; full custom logic cycling; self-timed bit-cycling; successive approximation register topology; synchronized sampling; time-interleaved SAR ADC; Application software; CMOS logic circuits; CMOS process; Capacitors; Clocks; Energy consumption; Logic arrays; Preamplifiers; Sampling methods; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
Conference_Location
San Jose, CA
Print_ISBN
0-7803-9023-7
Type
conf
DOI
10.1109/CICC.2005.1568690
Filename
1568690
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