• DocumentCode
    2908626
  • Title

    Improved scheduling of signal flow graphs onto multiprocessor systems through an accurate network modelling technique

  • Author

    Banerjee, Sati ; Picker, Dan ; Fellman, Ronald D. ; Chau, Paul M.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
  • fYear
    1994
  • fDate
    1994
  • Firstpage
    157
  • Lastpage
    167
  • Abstract
    This paper presents a new integrated technique for accurately scheduling acyclic precedence expansion graphs (APEGs) onto multiprocessor networks with various topologies. APEGs specify the nature, connectivity, and precedence relationships of all tasks, as well as data amounts that pass between tasks. We present a scheduling algorithm that uses the Branch and Bound technique when the number of tasks in the graph is small, and the Earliest Task First heuristic, otherwise. Graph partitioning and scheduling algorithms however, require a good estimate of interprocessor communication (IPC) costs within the target network. We thus use a technique called Successive Superposition to accurately determine IPC costs. Successive Superposition provides a methodology to decompose a complex network, containing primarily deterministic traffic, into simpler queueing models which may then be analyzed in isolation. By combining a heuristic scheduling algorithm with this exact IPC analysis technique, we avoid unpredictable behavior and incorrect mapping decisions that could result in longer graph execution times. We present an example in which an inaccurate assessment of IPC costs leads to a 22% to 30% increase in the graph execution time
  • Keywords
    signal flow graphs; acyclic precedence expansion graphs; branch and bound technique; deterministic traffic; earliest task first heuristic; graph partitioning; interprocessor communication costs; multiprocessor systems; network decomposition; network modelling; queueing models; scheduling algorithm; signal flow graphs; successive superposition; Costs; Digital signal processing chips; Flow graphs; Multiprocessing systems; Network topology; Partitioning algorithms; Processor scheduling; Scheduling algorithm; Telecommunication traffic; Traffic control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Signal Processing, VII, 1994., [Workshop on]
  • Conference_Location
    La Jolla, CA
  • Print_ISBN
    0-7803-2123-5
  • Type

    conf

  • DOI
    10.1109/VLSISP.1994.574740
  • Filename
    574740