TSV reduction in homogeneous 3D FPGAs by logic resource and input pad replication

One of the major challenges in the process of three-dimensional integrated circuit fabrication is the manufacturing of through silicon vias (TSV). These TSVs compared with other connection elements require high manufacturing costs as well as large silicon area. In this paper, replication technique has been used to reduce the number of TSVs in 3D FPGAs. Replication is implemented for circuit input pads and logic blocks. Experimental results over 20 MCNC benchmarks show 33% and 20% reduction in the number of TSVs and delay on average, respectively, at the cost of 3% more logic blocks and 3% more input pads that they place in the unused resources of FPGA.