Scarce-state-transition error-trellis decoding of binary block codes

A novel scarce-state-transition (SST) type Viterbi decoding system of block codes for discrete memoryless channels is proposed. In this work, we show that the SST-type Viterbi decoding system of convolutional codes devised by Kubota et al. (1986) can also be used to decode block codes. Like the SST-type Viterbi decoding of convolutional codes, the proposed system is well suited for CMOS LSI/VLSI implementation and has a lower power consumption. The implementation complexity is examined; the proposed decoding system has the same number of binary comparisons as the conventional Viterbi decoding system of block codes. Simulation results are presented for hard- and eight-level soft-decision decoding with BPSK modulation and coherent detection. Results show that the conventional Viterbi and the proposed SST-type Viterbi decoding systems give indistinguishable error performance for the same code