Interconnect design and analysis for Through Silicon Interposers (TSIs)

Author

Cubillo, Joseph Romen ; Weerasekera, Roshan ; Oo, Zaw Zaw ; Liu, En-Xiao ; Conn, Bob ; Bhattacharya, Surya ; Patti, Robert

Author_Institution

Inst. of Microelectron., A*STAR (Agency for Sci., Technol. & Res.), Singapore, Singapore

fYear

2012

fDate

Jan. 31 2012-Feb. 2 2012

Firstpage

1

Lastpage

6

Abstract

The trend of increasing digital system performance by downscaling the device size poses daunting challenges in system design due to the increased power density, higher I/O count, interconnect bandwidth, and timing closure requirements. Silicon carrier with Through Silicon Vias (TSVs) or TSI technology is identified as a system and packaging level solution to overcome all those challenges. In this paper we describe the key electrical elements in a typical TSI digital system and discuss their impact on overall system performance. We also discuss the system level power integrity analysis for TSI as its power delivery is one of the major engineering challenges.

Keywords

elemental semiconductors; integrated circuit bonding; integrated circuit interconnections; integrated circuit packaging; silicon; three-dimensional integrated circuits; Si; TSV technology; bandwidth interconnection; digital system performance; electrical elements; higher I/O count; interconnect design; power density; system level power integrity analysis; through silicon interposers; through silicon vias; timing closure requirements; typical TSI digital system; Delay; Field programmable gate arrays; Metals; Silicon; Through-silicon vias; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

3D Systems Integration Conference (3DIC), 2011 IEEE International

Conference_Location

Osaka

Print_ISBN

978-1-4673-2189-1

Type

conf

DOI

10.1109/3DIC.2012.6263039

Filename

6263039