VLSI Architectures for Lifting-Based Discrete Wavelet Packet Transform

In this paper, dedicated hardware implementations for discrete wavelet packet transform (DWPT) are investigated. After an intensive review of the exiting DWPT architectures, a folded architecture for lifting-based DWPT is proposed. Based on the previous pipeline DWPT architecture, this folded architecture reduces the hardware complexity significantly by folding multilevel DWPT decomposition into a single configurable processing element (PE). Compared with the conventional single-PE DWPT architecture, this folded architecture does not require extra memory to buffer the intermediate data during the DWPT computation and therefore avoids intensive memory access. Circuit simulation and implementation results demonstrate that the proposed folded architecture computes the multilevel DWPT much faster than the conventional single-PE architecture, while the hardware cost of the two architectures are almost identical.