DocumentCode
2908896
Title
Substrate noise analysis and experimental verification for the efficient noise prediction of a digital PLL
Author
Checka, Nisha ; Chandrakasan, Anantha ; Reif, Rafael
Author_Institution
Microsystems Technol. Labs., MIT, Cambridge, MA, USA
fYear
2005
fDate
18-21 Sept. 2005
Firstpage
473
Lastpage
476
Abstract
Substrate noise is a major impediment to mixed-signal integration. This paper describes a CAD tool that can be used at any stage of the design cycle to estimate the substrate noise generated by large digital circuits. The results have been verified with substrate noise measurements on a 480 MHz digital PLL implemented in a 90 nm CMOS process on a high resistivity substrate.
Keywords
CMOS digital integrated circuits; UHF integrated circuits; circuit CAD; circuit analysis computing; digital phase locked loops; integrated circuit noise; noise measurement; 480 MHz; 90 nm; CAD tools; CMOS process; digital PLL; digital circuits; high resistivity substrate; mixed-signal integration; noise prediction; substrate noise analysis; substrate noise measurements; Circuit noise; Circuit simulation; Circuit testing; Computational modeling; Digital circuits; Integrated circuit noise; Noise generators; Noise level; Phase locked loops; Phase noise;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
Print_ISBN
0-7803-9023-7
Type
conf
DOI
10.1109/CICC.2005.1568709
Filename
1568709
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