DocumentCode
2908971
Title
The Motorola 88110 Superscalar RISC microprocessor
Author
Diefendorff, Keith ; Allen, Michael
fYear
1992
fDate
24-28 Feb. 1992
Firstpage
157
Lastpage
162
Abstract
The Motorola 88110 is a second-generation, single-chip RISC (reduced instruction set computer) microprocessor that uses advanced techniques for exploiting instruction-level parallelism. Superscalar instruction issue, speculative execution, limited dynamic instruction recording and multiple on-chip caches are used to achieve high performance at a cost that makes it ideally suited as a central processor in low-cost personal computers and workstations. The advanced superscalar processor architecture and a high level of circuit integration have been implemented in a high-yield, triple-level metal, CMOS process using 1 mu design rules and requiring under 1.3 million transistors.<>
Keywords
CMOS integrated circuits; microcomputer applications; microprocessor chips; parallel architectures; reduced instruction set computing; CMOS process; Motorola 88110 Superscalar RISC microprocessor; advanced superscalar processor architecture; central processor; circuit integration; high performance; instruction-level parallelism; limited dynamic instruction recording; low-cost personal computers; multiple on-chip caches; reduced instruction set computer; single-chip RISC; speculative execution; triple-level metal; workstations; Circuits; Computer aided instruction; Computer architecture; Concurrent computing; Costs; Microcomputers; Microprocessors; Parallel processing; Reduced instruction set computing; Workstations;
fLanguage
English
Publisher
ieee
Conference_Titel
Compcon Spring '92. Thirty-Seventh IEEE Computer Society International Conference, Digest of Papers.
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-8186-2655-0
Type
conf
DOI
10.1109/CMPCON.1992.186702
Filename
186702
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