Energy-Efficient Input Buffer Design using Data-Transition Oriented Model

Network-on-chip (NoC) has been proved to be an efficient solution for interconnection between processor cores in chip multi-processor (CMP), which will consume extra energy. This paper is focusing on the energy-efficient design of input buffer, one of the most critical components in NoC. For precise calculation of energy, data-transition oriented model with multilevel simulations is proposed here. And using our method, a suit of benchmarks, SPLASH-2, are executed to evaluate the designs with different physical parameters and circuit structures. The simulations are based on 90 nm CMOS process, and the input buffer with 64-bit width and 16-entry depth is recommended for more energy-efficiency.