DocumentCode
2909085
Title
A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI
Author
Hamada, Mototsugu ; Hara, Hiroyuki ; Fujita, Tetsuya ; Teh, Chen Kong ; Shimazawa, Takayoshi ; Kawabe, Naoyuki ; Kitahara, Takeshi ; Kikuchi, Yu ; Nishikawa, Tsuyoshi ; Takahashi, Masafumi ; Oowaki, Yukihito
Author_Institution
SoC R&D Center, Toshiba Corp., Kawasaki, Japan
fYear
2005
fDate
18-21 Sept. 2005
Firstpage
527
Lastpage
530
Abstract
A novel conditional clocking flip-flop is proposed. The flip-flop circuit does not consume any power when the data input of the flip-flop does not change its state. Taking the overhead of the auxiliary circuits into account, the flip-flop consumes less power than the conventional flip-flop when the data transition probability is less than 55%. By employing the conditional clocking flip-flop circuits in a mobile applications LSI, the power consumption is reduced by 8-31%.
Keywords
audio coding; flip-flops; large scale integration; low-power electronics; power consumption; video codecs; audio/visual codec LSI; auxiliary circuits; conditional clocking flip-flop; data transition probability; flip-flop circuit; power consumption; Circuit testing; Clocks; Codecs; Delay; Energy consumption; Flip-flops; Large scale integration; Latches; MPEG 4 Standard; Master-slave;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
Print_ISBN
0-7803-9023-7
Type
conf
DOI
10.1109/CICC.2005.1568722
Filename
1568722
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