DocumentCode
2909098
Title
A VQ Algorithm Based on Novel Codebook and VLSI Architecture
Author
Dong-fang, WANG ; Yu-min, LIAO ; Ning-Mei, Yu
Author_Institution
Xi´´an Univ. of Technol., Xi´´an
fYear
2007
fDate
26-28 Sept. 2007
Firstpage
228
Lastpage
231
Abstract
A vector quantization (VQ) algorithm based on rotating compressed codebook is proposed. Compare with the typical vector quantization algorithm, the algorithm decreases 75% memory size and 75% input codebook bandwidth. The VLSI architecture for the algorithm was designed, and parallel pipeline was employed in the critical unit. The architecture was verified in FPGA, operation rate of the whole system can achieve 87.35 MHz. It can support real time application of 512times512 at 30 fps when the operation rate is 55 MHz.
Keywords
VLSI; field programmable gate arrays; image coding; integrated circuit design; integrated logic circuits; integrated memory circuits; logic design; pipeline processing; vector quantisation; FPGA; VLSI architecture; image coding; parallel pipeline architecture; rotating compressed codebook; vector quantization algorithm; Algorithm design and analysis; Bandwidth; Hardware; Image coding; Image reconstruction; PSNR; Pipelines; Testing; Vector quantization; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Circuits, 2007. ISIC '07. International Symposium on
Conference_Location
Singapore
Print_ISBN
978-1-4244-0797-2
Electronic_ISBN
978-1-4244-0797-2
Type
conf
DOI
10.1109/ISICIR.2007.4441839
Filename
4441839
Link To Document