CABAC HW Encoder with RDO Context Management and MBIST Capability

In this paper, a context-based adaptive binary arithmetic coding (CABAC) encoder architecture targeting H.264/AVC main profile is proposed. Pipeline structured encoder with FIFO buffers is designed to enhance coding efficiency, and coding speed of one symbol per cycle is achieved. Memory built-in-self-test (MBIST) circuit is also implemented in the encoder to provide testability of memory blocks. A context managing mechanism that fully supports RDO coding of H.264/AVC encoder is also designed, which significantly reduces context memory cost and operation delay for context backup and restore. The encoder is equipped with WISHBONE system bus interface to enhance reusability and integratability. Synopsys DC synthesis results show that the encoder can work at 760 MHz in normal condition targeting 0.13 mum CMOS process and the circuit occupies 27.1 K logic gates including 4.0 K gates of MBIST circuit.