Low-power, high-throughput deblocking filter for H.264/AVC

In this paper, we present a low-power, high-throughput hardware implementation of deblocking filter core in H.264/AVC for battery-powered multimedia electronic devices. The hardware implementation is based an optimized deblocking filter algorithm with 50% less number of addition operations. The evaluation of full or partial filtering skip scenarios is employed at an early stage in the filter processing chain to avoid un-necessary operations. Moreover, independent processing blocks are identified and are implemented with gated clock. Thus an efficient control block to activate/deactivate these independent processing blocks dynamically and pipeline implementation enable us to achieve low-power at one hand and high-throughput design for deblocking filter on the other. Experimental results suggest that the dynamic power consumption is reduced up to 50%, when compared with state-of-the-art designs in the literature. The deblocking filter core consumes 43 mW dynamic power on a Xilinx Virtex II FPGA and consumes 16.36 μW, when synthesized using 0.18 μm CMOS standard cell library. The FPGA implementation on Virtex II can work at 76 MHz whereas the maximum operating frequency for 0.18 μm process technology is 200 MHz. Our deblocking filter hardware implementation can easily provide real-time filtering operation for full-HD video format (1920×1080) @ 30 fps with an operating frequency as low as 59 MHz.