Wide Bandwidth Transconductor with Current Mode Feedback

Design guidelines for a recently proposed highly linear transconductor circuit are presented here, together with measurement results. Good linearity in the circuit is achieved by means of a low-gain current mode feedback that mitigates the impact of the non-linear dependence of i_DS on v_GS on the linearity of CMOS-based transconductance circuits by effectively attenuating the level of the capacitive distortion currents which typically have a significant detrimental impact on linearity in the upper frequency region, especially in op-amp based topologies. The G_m of the circuit is 160 muS and its OIP₃ is -49 dBA up to 60 MHz and decreases by 3 dB/octave thereafter. The output noise density is 15 pA/radicHz. The measured distortion and noise are well in line with the theory presented. The circuit was fabricated in 0.13 mum CMOS technology and consumed 1 mA from a 1.2 V supply. The core area of the G_m cell was 1000 mum².