A digit-set-interleaved radix-8 division/square root kernel for double-precision floating point

A common and very efficient approach to division and square root is the subtractive SRT algorithm combined with a redundant partial remainder representation like carry-save. A recently proposed modification of the SRT algorithm for division reduces the number of comparators inside the Quotient Digit Selection Function (QDSF) to the number necessary in a non-redundant implementation and derives partial remainders directly from comparison results calculated inside the QDSF. In this paper it is shown that this modified approach is also applicable to square root operations in an efficient way. A combined radix-8 division and square root kernel for double-precision floating point was synthesized using a 40-nm general-purpose cell library. The implementation comprises a critical path of only 20.8 fanout-4 inverter delays at worst case conditions which is comparable to 20.0 inverter delays published for a high-speed radix-4 SRT implementation. Furthermore, the proposed algorithm reduces the total area compared to equivalent SRT-based implementations.