RamLink: a high-bandwidth point-to-point memory architecture

Author

Gjessing, Stein ; Stone, Glen ; Wiggers, H.

Author_Institution

Oslo Univ., Norway

fYear

1992

fDate

24-28 Feb. 1992

Firstpage

328

Lastpage

331

Abstract

The authors describe RamLink, a memory interface architecture that allows RAM chips to be connected with point-to-point links in a ring topology. Low-voltage differential driver technology allows for very high throughput: 500 Mbytes/s on an 8-b-parallel data path. A RamLink memory subsystem consists of a memory controller and one or more (maximum 64) RamLink memory chips. A few RamLink chips, built from a conventional DRAM (dynamic RAM) process, provide a simple high-bandwidth memory subsystem. Preliminary simulations verify that the RamLink architecture has a very high system bandwidth with latency comparable to that of conventional memory systems. RamLink is inspired by the IEEE Scalable Coherent Interface specification (P1596) and has been authorized as an IEEE working group (P1596.4).<>

Keywords

peripheral interfaces; random-access storage; standards; 500 MByte/s; 8 bit; DRAM; IEEE Scalable Coherent Interface specification; P1596; RAM chips; RamLink; dynamic RAM; low voltage differential driver; memory chips; memory controller; memory interface architecture; memory subsystem; point-to-point links; point-to-point memory architecture; ring topology; system bandwidth; Bandwidth; Computer architecture; Computer interfaces; Costs; Delay; Memory architecture; Milling machines; Random access memory; Read-write memory; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Compcon Spring '92. Thirty-Seventh IEEE Computer Society International Conference, Digest of Papers.

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-8186-2655-0

Type

conf

DOI

10.1109/CMPCON.1992.186733

Filename

186733