Parallel adaptive algorithm for moving target indicator and its VLSI array realization

Author

Liu, Chi-Min ; Yang, Bor-Shyong ; Jen, Chein-Wei

Author_Institution

Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

1990

fDate

3-6 Apr 1990

Firstpage

1795

Abstract

A computationally efficient adaptive algorithm for the IBDA (innovations-based detection algorithm) is devised and realized with a systolic array so that is possesses both fast adaptation and good steady-state performance. The algorithm has superior numerical properties and computational complexity. It possesses high computing parallelism and good data locality, which are preferable in VLSI arrays. One systolic array example designed for the algorithm has an iteration time of (2N+1) and [(n²+3n)/2] processing elements, where n is the number of states

Keywords

VLSI; computational complexity; parallel algorithms; radar equipment; systolic arrays; IBDA; VLSI array realization; computational complexity; computationally efficient adaptive algorithm; computing parallelism; data locality; fast adaptation; innovations-based detection algorithm; iteration time; moving target indicator; numerical properties; processing elements; steady-state performance; systolic array; Adaptive algorithm; Adaptive arrays; Algorithm design and analysis; Clutter; Computational complexity; Concurrent computing; Detection algorithms; Filters; Parallel processing; Steady-state; Systolic arrays; Technological innovation; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1990. ICASSP-90., 1990 International Conference on

Conference_Location

Albuquerque, NM

ISSN

1520-6149

Type

conf

DOI

10.1109/ICASSP.1990.115837

Filename

115837